My PCI MDA got weirder.
10.03.2026 21:33
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My PCI MDA got weirder.
pretty close to that. blue is the diagonal, w/no runtime division.
thanks!
TubeTime’s monochrome display adapter core ported to my PCI FPGA VGA passthrough board. Maybe the first PCI MDA card. Full intensity is white, everything else is bitwise abuse of a rainbow pattern generator.
more of the 3D pipeline online
artifacting
have some glitch art.
I have no way to convey how strange it is for me to be able to see this from an FPGA.
for a 486/100, vlb was the same bus speed and width as pci, but on a processor local bus, instead of arbitration through the chipset.
Given a JTAG chain, walk the chain and map out the connections between all chips on the chain for which you have BSDL files (in this case, a configuration/flash mgmt CPLD and the FPGA it configures).
Given a JTAG chain, walk the chain and map out the connections between all chips on the chain for which you have BSDL files (in this case, a configuration/flash mgmt CPLD and the FPGA it configures).
The OpenOCD backend expands support past Altera FPGAs (and FPGAs in general).
The OpenOCD backend expands support past Altera FPGAs (and FPGAs in general).
it's in every chip
I’m building FPGA/PCB RE tools that actively probe a JTAG chain via OpenOCD or Altera’s AJI API using BSDL files. This script walks the chain, placing one device at a time into EXTEST, then samples boundary scan data long enough to identify pins carrying active clock signals.
very serious work is happening right now (sound on)
3,488 triangle edition of the Utah teapot, environment mapped by a hardware geometry engine through my recreation of the SST-1 fixed function pipeline. Important note: because it is the Utah teapot, the bottom is missing. Wouldn't be right to add it.
100% FPGA hardware. Entirely SystemVerilog.
one more use of the geometry engine, but first under simulation
the fjord torus’ geometry engine was a fun detour for debugging.
next stop: bus w/software doing the driving
made a gif for the github page
hp color recovery doing 1080p44 out of a 2MB sram
decided to become a not-quite-anon after reading pastebin.com/Ft7P5m9F
Been chewing on what to put in README․md with AI in the loop.
Presenting the AI CODING ADVISORY SYSTEM. Useful labels for whatever the heck I just built.
timing glitch art (free to a good home)
I don’t have the BRAM for a depth buffer so it’s time to get the memory controller up and running for this fjord torus.
100% FPGA logic 3D pipeline, no CPU.
interested in the cosim infra
looks like it works now
the 3d rast pipeline is a tools-assisted speedrun. the combo of claude code + codex is turning what would have taken years into months.
maybe after I'm done with it
