arXiv cs.AR Hardware Architecture

Gunawardana, Peeris, Rambukwella, Wanduragala, Jameel, Ragel, Nawinne: SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks https://arxiv.org/abs/2603.11939 https://arxiv.org/pdf/2603.11939 https://arxiv.org/html/2603.11939

Axel Vanoni, Philippe Sauter, Paul Scheffler, Anton Buchner, Micha Wehrli, Thomas Benz, Luca Benini: Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs https://arxiv.org/abs/2603.11849 https://arxiv.org/pdf/2603.11849 https://arxiv.org/html/2603.11849

Aaron Yen, Jooyeon Jeong, Puneet Gupta: Link Quality Aware Pathfinding for Chiplet Interconnects https://arxiv.org/abs/2603.11612 https://arxiv.org/pdf/2603.11612 https://arxiv.org/html/2603.11612

Fu, Wang, Shao, Karri, Shafique, Knechtel, Sinanoglu, Guo: Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes https://arxiv.org/abs/2603.11287 https://arxiv.org/pdf/2603.11287 https://arxiv.org/html/2603.11287

Runbang Hu, Bo Fang, Bingzhe Li, Yuede Ji: Unifying Logical and Physical Layout Representations via Heterogeneous Graphs for Circuit Congestion Prediction https://arxiv.org/abs/2603.11075 https://arxiv.org/pdf/2603.11075 https://arxiv.org/html/2603.11075

[2026-03-13 Fri (UTC), 5 new articles found for csAR Hardware Architecture]

Qiyue Chen, Yao Li, Jie Tao, Song Chen, Li Li, Dong Liu: An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS https://arxiv.org/abs/2603.10671 https://arxiv.org/pdf/2603.10671 https://arxiv.org/html/2603.10671

Shuai Dong, Junyi Yang, Biyan Zhou, Hongyang Shang, Gourav Datta, Arindam Basu: In-Memory ADC-Based Nonlinear Activation Quantization for Efficient In-Memory Computing https://arxiv.org/abs/2603.10540 https://arxiv.org/pdf/2603.10540 https://arxiv.org/html/2603.10540

Ma, Ma, Su, Zha, Zhao, Shang, Yi, Liu, Cao, Wu, Dou, Liu, Kuang, Luo: Pooling Engram Conditional Memory in Large Language Models using CXL https://arxiv.org/abs/2603.10087 https://arxiv.org/pdf/2603.10087 https://arxiv.org/html/2603.10087

Zhongming Yu, Naicheng Yu, Hejia Zhang, Wentao Ni, Mingrui Yin, Jiaying Yang, Yujie Zhao, Jishen Zhao: Multi-Agent Memory from a Computer Architecture Perspective: Visions and Challenges Ahead https://arxiv.org/abs/2603.10062 https://arxiv.org/pdf/2603.10062 https://arxiv.org/html/2603.10062

Shubham Kumar Singh: HTM-EAR: Importance-Preserving Tiered Memory with Hybrid Routing under Saturation https://arxiv.org/abs/2603.10032 https://arxiv.org/pdf/2603.10032 https://arxiv.org/html/2603.10032

Athos Georgiou: Architecture-Aware LLM Inference Optimization on AMD Instinct GPUs: A Comprehensive Benchmark and Deployment Study https://arxiv.org/abs/2603.10031 https://arxiv.org/pdf/2603.10031 https://arxiv.org/html/2603.10031

Marco Graziano: The DMA Streaming Framework: Kernel-Level Buffer Orchestration for High-Performance AI Data Paths https://arxiv.org/abs/2603.10030 https://arxiv.org/pdf/2603.10030 https://arxiv.org/html/2603.10030

Xinsheng Tang, Yangcheng Li, Nan Wang, Zhiyi Shu, Xingyu Ling, Junna Xing, Peng Zhou, Qiang Liu: RedFuser: An Automatic Operator Fusion Framework for Cascaded Reductions on AI Accelerators https://arxiv.org/abs/2603.10026 https://arxiv.org/pdf/2603.10026 https://arxiv.org/html/2603.10026

[2026-03-12 Thu (UTC), 8 new articles found for csAR Hardware Architecture]

Yang, Tan, Hu, Gao, Liu, Jiang, Chen, Long, Lv, Shu: Nemo: A Low-Write-Amplification Cache for Tiny Objects on Log-Structured Flash Devices https://arxiv.org/abs/2603.09605 https://arxiv.org/pdf/2603.09605 https://arxiv.org/html/2603.09605

Wang, Jung, Wiese, Conti, Burrello, Benini: TrainDeeploy: Hardware-Accelerated Parameter-Efficient Fine-Tuning of Small Transformer Models at the Extreme Edge https://arxiv.org/abs/2603.09511 https://arxiv.org/pdf/2603.09511 https://arxiv.org/html/2603.09511

Musa Cim, Burak Topcu, Mahmut Taylan Kandemir: Diagnosing FP4 inference: a layer-wise and block-wise sensitivity analysis of NVFP4 and MXFP4 https://arxiv.org/abs/2603.08747 https://arxiv.org/pdf/2603.08747 https://arxiv.org/html/2603.08747

Ming-Yen Lee, Shimeng Yu: ChatNeuroSim: An LLM Agent Framework for Automated Compute-in-Memory Accelerator Deployment and Optimization https://arxiv.org/abs/2603.08745 https://arxiv.org/pdf/2603.08745 https://arxiv.org/html/2603.08745

Keita Morisaki: The AetherFloat Family: Block-Scale-Free Quad-Radix Floating-Point Architectures for AI Accelerators https://arxiv.org/abs/2603.08741 https://arxiv.org/pdf/2603.08741 https://arxiv.org/html/2603.08741

Soumita Chatterjee, Sudip Ghosh, Tamal Ghosh, Hafizur Rahaman: Architectural Design and Performance Analysis of FPGA based AI Accelerators: A Comprehensive Review https://arxiv.org/abs/2603.08740 https://arxiv.org/pdf/2603.08740 https://arxiv.org/html/2603.08740

Zheng, Wang, Ma, Wang, Wang, Chen, Zhang, Pan, Huang, Wu, Zhang, Cai, Liu, Ma, Du, Deng, Wu, Zhu, Zhang, Li: Adaptive Multi-Objective Tiered Storage Configuration for KV Cache in LLM Service https://arxiv.org/abs/2603.08739 https://arxiv.org/pdf/2603.08739 https://arxiv.org/html/2603.08739

Kezhi Li, Min Li, Xiangyu Wen, Shibo Zhao, Jieying Wu, Junhua Huang, Qiang Xu: FormalRTL: Verified RTL Synthesis at Scale https://arxiv.org/abs/2603.08738 https://arxiv.org/pdf/2603.08738 https://arxiv.org/html/2603.08738

Atousa Jafari, Mahdi Taheri, Hassan Ghasemzadeh Mohammadi, Christian Herglotz, Marco Platzner: Sensitivity-Guided Framework for Pruned and Quantized Reservoir Computing Accelerators https://arxiv.org/abs/2603.08737 https://arxiv.org/pdf/2603.08737 https://arxiv.org/html/2603.08737

Sangkeum Lee: Measurement-Free Ancilla Recycling via Blind Reset: A Cross-Platform Study on Superconducting and Trapped-Ion Processors https://arxiv.org/abs/2603.08733 https://arxiv.org/pdf/2603.08733 https://arxiv.org/html/2603.08733

Vincenzo Liguori: Fair and Square: Replacing One Real Multiplication with a Single Square and One Complex Multiplication with Three Squares When Performing Matrix Multiplication and Convolutions https://arxiv.org/abs/2603.08732 https://arxiv.org/pdf/2603.08732 https://arxiv.org/html/2603.08732

Jianlong Lei, Shashikant Ilager: ARKV: Adaptive and Resource-Efficient KV Cache Management under Limited Memory Budget for Long-Context Inference in LLMs https://arxiv.org/abs/2603.08727 https://arxiv.org/pdf/2603.08727 https://arxiv.org/html/2603.08727

Tobias Habermann, Martin Kumm: Data-Rate-Aware High-Speed CNN Inference on FPGAs https://arxiv.org/abs/2603.08726 https://arxiv.org/pdf/2603.08726 https://arxiv.org/html/2603.08726

Luigi Capogrosso, Pietro Bonazzi, Michele Magno: Performance Analysis of Edge and In-Sensor AI Processors: A Comparative Review https://arxiv.org/abs/2603.08725 https://arxiv.org/pdf/2603.08725 https://arxiv.org/html/2603.08725

Mahdi Taheri: PhD Thesis Summary: Methods for Reliability Assessment and Enhancement of Deep Neural Network Hardware Accelerators https://arxiv.org/abs/2603.08724 https://arxiv.org/pdf/2603.08724 https://arxiv.org/html/2603.08724