Latest posts tagged with #FlowPPU on Bluesky
We’re grateful to the SemiTO-V Student Team & the organizers for bringing us together to discuss the future of #HPC These conversations are important inshaping next-gen compute architectures. More events are coming soon: flow-computing.com/events/
#RISCV #CPU #Semiconductors #FlowPPU #DeepTech
Read the full article ↓
viewpoints.fov.ventures/p/europe-s-d...
#DeepTech #EuropeanTech #AI #Semiconductors #ParallelProcessing #Robotics #SpatialComputing #FlowComputing #FlowPPU #VentureCapital #VC
Research in shared-memory systems, interconnection networks, and compiler techniques for explicit parallelism drive the #FlowPPU. The result is TCF, a programming and execution model that simplifies parallel software development. See the science behind Flow: flow-computing.com/science/
#CPU #HPC
We’re 2! Over the past 2 years, we’ve been developing #FlowPPU, a licensable co-processor designed to unlock efficient, general-purpose parallel execution across architectures. Thank you to our team, partners, & investors for being part of our journey.
#DeepTech #Semiconductors #Startup #HPC #CPU
Close-up illustration of a processor on a circuit board. Text explains that overall performance depends on CPU-side parallelism, data preparation, pipeline efficiency, synchronization, and throughput per watt. Source: Arm / Futurum Research, 2026.
Slide titled “Scaling AI requires scaling parallel execution inside the CPU,” with a minimalist 3D chip illustration.
Slide titled “Flow PPU enables.” Key points: scalable general-purpose parallel throughput inside the CPU, more efficient execution of data-intensive workloads, improved CPU throughput to reduce accelerator bottlenecks, and ISA-independent integration across x86, Arm, RISC-V, and OpenPOWER.
Accelerators deliver raw compute. System throughput determines performance. Learn how #FlowPPU enables scalable parallel throughput inside the #CPU:
flow-computing.com/science/
Source: Arm / @futurumgroup.bsky.social
research, 2026
#DeepTech #Semiconductors #AI #Datacenter #HPC #arm #Futurum
Black-and-white four-panel portrait collage of Flow team members with quotes about building an international engineering team across Europe. Center badge reads “Parallel Perspectives - Flow.” Text highlights attracting talent across Europe and scaling collaboration efficiently.
During #engineeringweek we're showing the people behind our tech. In #Podcast Ep 3, the team shares how we’re building a pan-European team, & why the best talent isn’t found in 1 place. Listen to the full ep: flow-computing.com/parallel-per...
#DeepTech #Semiconductors #CPU #HPC #FlowPPU
As accelerator performance scales, overall system efficiency increasingly depends on #CPU throughput, data preparation & orchestration. Deep dive into our architecture:
flow-computing.com/science
@semianalysis.skystack.xyz
#AI #Datacenter #Semiconductors #HPC #DeepTech #FlowComputing #FlowPPU
Minimal grey slide with Flow logo and headline: “AI is increasing pressure on datacenter CPUs.” Subtext reads: “Signals from recent industry analysis (SemiAnalysis, 2026).” A rounded button says “What’s driving it?”
Slide titled “What’s driving CPU demand” with a datacenter image showing a person monitoring equipment. Key points: reinforcement learning requires large CPU clusters; agents, RAG, and tool use increase general-purpose compute; CPUs handle data preparation, indexing, decoding, and orchestration; large CPU fleets keep GPU clusters fully utilized. Source: SemiAnalysis, 2026.
Slide titled “Scaling CPUs isn’t simpler” with abstract chip-like background. Key points: core counts are rising but interconnect and memory behavior matter more; latency, coherence, and NUMA effects become major constraints; feeding accelerators reliably becomes the system bottleneck.
Slide titled “A better way to scale CPU performance” with illustration of a CPU and Flow PPU chip. Text explains that Flow PPU enables scalable parallel execution inside the CPU by offloading parallel workloads without increasing core count, enabling linear scaling for data-intensive tasks, improving throughput to reduce system bottlenecks, and supporting x86, Arm, RISC-V, and OpenPOWER architectures.
#AI workloads are changing the role of the #datacenter #CPU. Recent analysis from @semianalysis.skystack.xyz shows rising CPU demand driven by RL environments, agentic workflows, & data-intensive pipelines.
@semianalysis.com.web.brid.gy
#Semiconductors #HPC #DeepTech #FlowComputing #FlowPPU
Great discussions, strong momentum, and a productive week together.🦾 #FlowComputing #FlowPPU #CPU #HPC #DeepTech #Semiconductors #CompilerEngineering #Maria01
Flow Computing team members sitting together on a sofa in a modern office lounge, smiling toward the camera in a collaborative workspace environment.
Part of the team met in #Helsinki for focused collaboration. We're glad Hugo Pompougnac & Jordi Sala Juárez joined the sessions stepping Senior Compiler Engineers roles. Building next-gen #CPU performance requires close alignment. Strengthening our compiler team is important as we develop #FlowPPU.
This is what makes #FlowPPU relevant across a wide range of compute environments.
Full conversation↓
flow-computing.com/interviews/
@kpmgus.bsky.social , @kpmgusnews.bsky.social @kpmguk.bsky.social
#Semiconductors #DeepTech #AIInfrastructure #HPC #CPU #FlowPPU #FlowComputing #KPMG
KPMG Private Enterprise Global Tech Innovator 2025 title screen introducing the interview featuring Flow Computing.
Michael Bancroft from Beyond Innovation interviewing about Flow Computing’s licensable processor technology and CPU performance innovation.
Timo Valtonen, CEO and co-founder of Flow Computing, discussing Flow PPU and the role of speed and parallel processing in next-generation CPUs.
NextGen performance comes from how efficiently parallel work happens inside CPUs. #FlowPPU is built around this: #ParallelProcessing integrates directly into the #CPU; Works across architectures - x86, arm, @riscv.org.web.brid.gy, OpenPower; Configurable for different targets (hyperscale - edge).
Sala Emma Strada, #PolitecnicodiTorino
Feb 26, 2026, 15:35-16:00
Register below↓ community.riscv.org/events/detai...
@riscv.org.web.brid.gy @riscvinternational.bsky.social @riser-project.bsky.social
#RISCV #RISCVDays #FlowPPU #CPU #DeepTech #HPC #Semicondcutors
Promotional graphic announcing Marcello Ranone, Head of CPU Development at Flow Computing, speaking at World RISC-V Days in Turin on February 26, 2026. The graphic includes a black-and-white portrait of Marcello Ranone, Head of CPU Development, Flow Computing logo, the talk title “The PPU Technology of Flow Computing,” the session time 15:35-16:00, and the venue Sala Emma Strada at Politecnico di Torino, with RISC-V and Politecnico di Torino logos.
Marcello will speak @ World #RISC-VDays in Turin on Feb 26. He'll present The PPU Technology of Flow Computing, covering how #FlowPPU enables scalable parallel performance while remaining instruction-set independent, working alongside modern #CPU architectures including #RISCV.
You can’t trust everyone.
You can trust the architecture.
Flow PPU → scalable parallel performance
The science behind it → flow-computing.com/SCIENCE/
#ComputerArchitecture #ParallelComputing #FlowPPU #DeepTech #CPU #HPC #Semiconductor
Black-and-white group photo of Flow Computing founders and team leads gathered during an in-person alignment session in Oulu, Finland.
Recently in cool Oulu. Our founders + Gábor Márton, PhD, & Marcello Ranone, spent time in person aligning on priorities & brainstorming on the next steps. Yes, there was time for a sauna by the #Oulu river & dipping into ice-cold avanto too. (At -21°C.)
#FlowPPU #DeepTech #Semiconductor #CPU #HPC
ISA independence gives long-term optionality. Open standards like RISC-V make that optionality real.
@riscv.org.web.brid.gy, @riser-project.bsky.social
#OpenSource #RISCV #ComputerArchitecture #FlowPPU #CPU #DeepTech #HPC #Semiconductor
Diagram-style graphic with the text “Flow PPU is designed to integrate with CPUs across instruction sets,” with logos for Arm, AMD, Intel, RISC-V, and OpenPOWER shown as example CPU ecosystems, highlighting Flow’s instruction-set-independent PPU architecture.
#FlowPPU is instruction set independent, enabling integration across different #CPU ecosystems w/o locking performance gains to a single ISA. #RISCV is our 1st supported architecture bc its open standard, tooling, & community align w/ this philosophy + accelerate both innovation & collaboration.
Thank you to #Maria01. We are proud to be part of your community.🌟
#StartUp #Helsinki #Finland #DeepTech #PPU #FlowPPU #CPU #HPC
In 2025, we were named a #Maria01 Rising Star & is featured on the Hall of Fame wall. The recognition highlights early-stage companies building technology w/ long-term impact.
#Helsinki #StartUp #Finland #DeepTech #PPU #FlowPPU #CPU #HPC
Stylized image of a CPU integrated into a circuit board, with illuminated data paths emphasizing system architecture, overlaid with the text “Performance is an architectural decision.”
Modern CPUs aren’t just limited by core counts. They’re limited by how well memory, synchronization, & #parallelexecution are handled at the architectural level. #FlowPPU combines decades of parallel computing research, w/ a design that emphasizes scalable throughput & simpler parallel programming.
