#zen2

InstLatX64

@instlatx64.bsky.social

3 weeks ago

This snow report was the inspiration for this #AMD #Zen codename table. Sources included.
#Zen2 #Zen3 #Zen4 #Zen5 #Zen6 #Zen7

pyramidplayer1

@pat-hammond.bsky.social

3 months ago

Monday’s Zendo challenge went really well 😊👍 Here’s another from the PA deck. This one is a medium difficulty level.

#LooneyPyramids #boardgames #zen2

Fell

@fell.ma.fellr.net.ap.brid.gy

8 months ago

Does anyone know more about the Linux scheduler? Like, how does it behave when some tasks are pinned to certain cores while others are not? Does other tasks natually tend to stay away from those "reserved" cores?

I would appreciate any resources on this topic. It's interesting.

3/3

#Hardware […]

Fell

@fell.ma.fellr.net.ap.brid.gy

8 months ago

Screenshot of the "lstopo" utility. It displays a block diagram of the CPU topology. There are various rectangles of slightly different colour. There are 12 cores with 2 threads each, but the cores are organised in 4 chunks of 3. Each chunk shares 16 MB of L3 cache.

I always wondered why my 3900X with 64 MB of cache performs so much worse than a 5700X3D with 96 MB of cache. It's only ⅓ more cache, after all.

Well, `lstopo` had the answer. The cache is split into 4 chunks (CCXs), so a single thread only really has 16 MB of […]

[Original post on ma.fellr.net]

InstLatX64

@instlatx64.bsky.social

1 year ago

Unfortunately the diagram was wrong, hopefully it's correct now: based on the current #AMD #EPYC 9965 dump, the #Zen5 also shifts the APIC bits to right in case of SMT-off, like the #Zen2 and #Zen3 (and unlike #Zen4)
EPYC 9965: github.com/InstLatx64/I...